The XPI handles the common response interface to the DDRC to process the read data from the memory. AXI read data and response channel has a single-data storage queue, the read data queue (RDQ). Data from different IDs are stored in the same queue and are returned in the order of read-address acceptance. The controller provides an OKAY response for each read, except for exclusive read transactions. A SLVERR response can be returned for read transactions (both normal and exclusive) in the following cases.
•ECC uncorrected error detected at the DFI.
•Invalid LPDDR3 row address.
•Transaction is poisoned.
The read data can be returned from the DDRC in a different order from the order that the read commands are forwarded from the XPI. This is due to the re-ordering of read commands in the DDRC to maximize SDRAM bandwidth. A read reorder buffer is implemented in each port to reorder the read data for that port to the same order as the order of the AXI read commands. The read reorder buffer SRAM holds the same number of entries as the read CAM and each entry holds the read data corresponding to a DDR command. The AXI protocol allows the read data for transactions of different IDs to be interleaved. To reduce potential delays where read data for one ID is blocked waiting for data associated with another ID, the read reorder buffer is organized in number of virtual channels. The read reorder virtual channel (RRVC) is a mechanism to allow independent read data reordering between multiple groups of AXI IDs.