Read Leveling

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The read DQS strobes from the DRAM are ordinarily gated by the PHY to suppress noise and correctly capture read data. The precise alignment of the gate to the read data is a prerequisite for proper reads. Since delays, such as board trace lengths in the read path, are often imprecisely known, it is necessary to train the gate for a particular system. The PHY features a built-in read DQS strobe gate training unit that might be triggered as part of the initialization process.

Read leveling is an algorithm that works with the edge of the DQS. Gate and a delayed (by a few LCDL taps) gate sample the DQS signal. Gate starts from (a position of delay equal to zero) until the first edge of the DQS is found between the two sampling edges of the gate and delayed gate. Final position of the gate is found by adding a programmable (delay) offset to this value.

The completion of read leveling is signaled by PGSR0.QSGDONE. PGSR0.QSGERR indicates that an error occurred during read leveling. Errors are flagged in the DATX8 Rank Status register 1, as listed in Table: DATX8 Rank Status Register 1 (DXnRSR1).

Table 17-13:      DATX8 Rank Status Register 1 (DXnRSR1)

Register

Bits

Name

Description

Address

DX0RSR1

[1:0]

RDLVLERR

Read leveling error: if set, indicates that there is an error in read leveling training of byte 0. One bit for each of the up to two ranks.

0xFD0807D4

DX1RSR1

[1:0]

RDLVLERR

Same as above, for byte 1.

0xFD0808D4

DX2RSR1

[1:0]

RDLVLERR

Same as above, for byte 2.

0xFD0809D4

DX3RSR1

[1:0]

RDLVLERR

Same as above, for byte 3.

0xFD080AD4

DX4RSR1

[1:0]

RDLVLERR

Same as above, for byte 4.

0xFD080BD4

DX5RSR1

[1:0]

RDLVLERR

Same as above, for byte 5.

0xFD080CD4

DX6RSR1

[1:0]

RDLVLERR

Same as above, for byte 6.

0xFD080DD4

DX7RSR1

[1:0]

RDLVLERR

Same as above, for byte 7.

0xFD080ED4

DX8RSR1

[1:0]

RDLVLERR

Same as above, for ECC byte.

0xFD080FD4

Additional read leveling debugging information is listed in Table: Read Leveling Debug Registers.

Table 17-14:      Read Leveling Debug Registers

Register

Bits

Name

Description

Address

DX0GSR0

[25:17]

GDQSPRD

Read DQS gating period: returns the DDR clock period measured by the read DQS gating LCDL during calibration of byte 0. This value is PVT compensated.

0xFD0807E0

DX1GSR0

[25:17]

GDQSPRD

Same as above, for byte 1.

0xFD0808E0

DX2GSR0

[25:17]

GDQSPRD

Same as above, for byte 2.

0xFD0809E0

DX3GSR0

[25:17]

GDQSPRD

Same as above, for byte 3.

0xFD080AE0

DX4GSR0

[25:17]

GDQSPRD

Same as above, for byte 4.

0xFD080BE0

DX5GSR0

[25:17]

GDQSPRD

Same as above, for byte 5.

0xFD080CE0

DX6GSR0

[25:17]

GDQSPRD

Same as above, for byte 6.

0xFD080DE0

DX7GSR0

[25:17]

GDQSPRD

Same as above, for byte 7.

0xFD080EE0

DX8GSR0

[25:17]

GDQSPRD

Same as above, for byte 8.

0xFD080FE0

DX0GTR0

[4:0]

DGSL

DQS gating system latency: this is used to increase the number of clock cycles need to expect valid DDR read data for byte 0. This is used to compensate for board delays and other system delays. Power-up default is 0x00 (i.e., no extra clock cycles required). Valid values are 0 to 18 and each increment adds a half SDRAM CK period.

0xFD0807C0

DX1GTR0

[4:0]

DGSL

Same as above, for byte 1.

0xFD0808C0

DX2GTR0

[4:0]

DGSL

Same as above, for byte 2.

0xFD0809C0

DX3GTR0

[4:0]

DGSL

Same as above, for byte 3.

0xFD080AC0

DX4GTR0

[4:0]

DGSL

Same as above, for byte 4.

0xFD080BC0

DX5GTR0

[4:0]

DGSL

Same as above, for byte 5.

0xFD080CC0

DX6GTR0

[4:0]

DGSL

Same as above, for byte 6.

0xFD080DC0

DX7GTR0

[4:0]

DGSL

Same as above, for byte 7.

0xFD080EC0

DX8GTR0

[4:0]

DGSL

Same as above, for byte 8.

0xFD080FC0

DX0LCDLR2

[8:0]

DQSGD

DQS gating delay: delay select for the DQS gating (DQSG) LCDL for byte 0.

0xFD080788

DX1LCDLR2

[8:0]

DQSGD

Same as above, for byte 1.

0xFD080888

DX2LCDLR2

[8:0]

DQSGD

Same as above, for byte 2.

0xFD080988

DX3LCDLR2

[8:0]

DQSGD

Same as above, for byte 3.

0xFD080A88

DX4LCDLR2

[8:0]

DQSGD

Same as above, for byte 4.

0xFD080B88

DX5LCDLR2

[8:0]

DQSGD

Same as above, for byte 5.

0xFD080C88

DX6LCDLR2

[8:0]

DQSGD

Same as above, for byte 6.

0xFD080D88

DX7LCDLR2

[8:0]

DQSGD

Same as above, for byte 7.

0xFD080E88

DX8LCDLR2

[8:0]

DQSGD

Same as above, for byte 8.

0xFD080F88