Read Status

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English
Table 25-10:      Read Status

Task

Register

Register Field

Register Offset

Bits

Value (Binary)

Enable transfer complete interrupt.

Interrupt_Status_Enable_Register

trans_comp_sts_en

0x014

2

1b'1

Program command for read status (0x70).

Command_Register

All

0x0C

31:0

0x00000070

Select the device.

Memory_Address_Register2

Chip_Select

0x08

31:30

Targets chip select value.

Program packet size and packet count.

Packet_Register

Packet_count | packet_size

0x00

23:0

Required packet size and count.

Set status in program register.

Program_Register

Read_Status

0x10

3

1b'1

Poll for transfer complete event.

Interrupt_Status_Register

trans_comp_reg

0x1C

2

Wait until transfer is completed or wait time is over.

Clear the transmit complete interrupt after transfer completed.

Interrupt_Status_Enable_Register

trans_comp_sts_en

0x014

2

1b'0

Clear the transmit complete flag after transfer completed.

Interrupt_Status_Register

trans_comp_reg

0x1C

2

1b'1

Read flash status register.

Flash_Status_Register

Flash_Status

0x28

15:0

Read operation.