The HP interfaces provide 128-entry deep data buffers for each read and write data channel. The HP interfaces also provide buffer level information via count ports. The read data buffer information level is used when the PL-master data consumer logic is decoupled from the read request logic. Similarly, the write data buffer level information is used when the PL-master write data producer logic streams out data before a write request is generated.
The read data buffer is used as a pre-allocation or pre-fetch buffer, where the PL can issue a large number of read requests without having its own read pre-allocation or pre-fetch buffer. The write data buffer is used to stream the write data before a write request.
Based on the relative levels of the count values provided, a PL controller can dynamically change the priority of the individual read and write requests into the high-performance AXI interface block(s). The FIFO level count should be used as a relative level, as opposed to an exact level, because clock domain crossing is involved.