Read/Write Arbitration

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The main goal of the read/write arbitration is to combine reads and writes together as long as the selected direction has available credits and the timeout has not occurred for any port of the opposite direction. If all conditions are equal, reads are prioritized over writes. Minimizing direction switches improves memory bus efficiency.

For example while executing reads, stay on the reads as long as there is a timed-out read port or expired video/isochronous priority reads (VPR) with available credit, else switch to writes if there is a timed-out write port or expired video/isochronous priority writes (VPW) with available credit. Otherwise, switch to writes when there is no read-credit left and there is a pending write with available credit.

While executing writes, stay on the writes as long as there is a timed-out write port or expired-VPW with available credit, else switch to reads if there is a timed-out read port or expired-VPR with available credit. Otherwise, switch to reads if there is an HPR read port with available credit, else switch to reads when there is no write-credit left and there is a pending read with available credit.

The timeouts are implemented using aging counters implemented per port, per direction that count down the time when a port is requesting but not granted. The timeout condition occurs when a port aging counter becomes 0 and the port becomes the highest priority requester (priority 0) to the port arbiter. The PCFGR [rd_port_priority] and PCFGW [wr_port_priority] register bits determine the initial value of the counters. The aging feature and the timeout are enabled by the PCFGR [rd_port_aging_en] and PCFGW [wr_port_aging_en] register bits.