Receive Buffer Descriptor List

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The data received by the controller is written to pre-allocated buffer descriptors in system memory. These buffer descriptor entries are listed in the receive buffer queue. Refer to DMA Controller and Table: RX Buffer Descriptor Entry for more information on implementation and structure of the RX buffer descriptor.

The receive-buffer queue pointer registers (gem.receive_q{ , 1}_ptr) points to this data structure as shown in This Figure.

Figure 34-13:      RX Buffer Queue Structure

X-Ref Target - Figure 34-13

X15517-rx-buffer-structure.jpg

To create a list of buffers:

1.Allocate a number (N) of buffers of X bytes in system memory, where X is the DMA buffer length programmed in the DMA configuration register.

Example: This controller assumes that the maximum size of an Ethernet packet without jumbo frame support can reach up to x bytes. Allocate N number of buffers each with a size of 1,536 bytes in system memory. The buffers typically need to be aligned to cache-line boundaries to improve performance. Typical values of N can be 64 or 128.

2.Each buffer descriptor length is 8 bytes. Allocate an area of 8N bytes for the receive buffer descriptor list in system memory. This creates N entries in this list.

 

RECOMMENDED:   A single cache line for the APU L2 cache is 64 bytes and can contain 8 buffer descriptors. This means flushing or invalidating a single buffer descriptor entry in the cache memory results in flushing or invalidation of a cache line which in turn affects the adjacent buffer descriptors. This can result in undesirable behavior. It is typical to allocate the buffer descriptor list in an un-cached memory region.

3.Mark all entries in this list as owned by controller. Set bit [0] of word [0] of each buffer descriptor to 0.

4.Mark the last descriptor in the buffer descriptor list with the wrap bit, (bit [1] in word [0]) set.

5.Fill the addresses of the allocated buffers in the buffer descriptors (bits [31-2], Word [0])

6.Write the base address of this buffer descriptor list to the gem.receive_q{ , 1}_ptr registers.

Note:   See the Q pointer note under Initialize the Controller.