Receive Clock Tap Delay

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The RX clock delay is used for tuning/delaying the receive clock so as to align the clock in the center of the data window. This is used in both auto tuning (in SDR50 and SDR104 mode) and optional manual tuning (for high-speed modes such as DDR).

During read operation, the host controller acts as a receiver, and the data might not be exactly aligned with respect to the clock. The clock signal can be delayed either by auto tuning or manual tuning so that the clock is center aligned to receive data.

For SDR104 mode and for SDR50 mode, automatic tuning is performed and the external controls are cleared i.e., sd{0,1}_itapdlyena is reset. The host controller has an algorithm to correctly find the center of the eye for better timing. The tuning procedure selects one phase of the clock (rxclk_in) for each iteration. At the end of tuning, the right phase of the clock is selected that is in the center of the data.

In other modes (such as DDR50), the manual tuning of the SD_CLK (rxclk_in) can be performed using the external controls.

sd{0,1}_itapdlysel [7:0]: Used to select the optimum delay from 30 to 180 tap delay lines.

sd{0,1}_itapdlyen: Used to enable the input tap delay.

The clock delay can be imposed by either using tap delay or a DLL that generates multiple phases of the clock. The maximum number of phases (tap delay) supported is 180, even though the typical number of phases (tap delay) is four or eight.

This Figure shows the usage of the DLL for the TX CMD/DAT delay and the RX clock tap delay.

Figure 26-4:      SD Clock Control Using Existing DLL

X-Ref Target - Figure 26-4

X15449-sd-dll-block.jpg

The block diagram (This Figure) is further described in this section.

The DLL has the DLL_REF_CTRL.srcsel[2:0], clkctrl_sdclkfreqsel[7, 6,15:8], SD{0,1}_ITAPDLYSEL[7:0], and SD{0,1}_OTAPDLYSEL[5:0] register controls.

DLL clock can be generated based on the DLL_REF_CTRL.srcsel[2:0] and DLL divisor value. This DLL divisor internally selects based on the clkctrl_sdclkfreqsel[7, 6,15:8] value from the reg_clockcontrol register of SDI{0,1}. For example, the DLL is derived from the IOPLL (Table: DLL Mode Supported Clocks).

Table 26-4:      DLL Mode Supported Clocks

SD{0,1}_BASECLK (MHz)

DLL (MHz)
IOPLL or RPLL

clkctrl_sdclkfreqsel

Actual DLL Divider Value

SD Output Frequency (MHz)

200

1500

0

7.5

200

1500

1

15

100

1500

2

30

50

1500

3

45

33.33

100

1500

0

15

100

1500

1

30

50

50

1500

0

30

50

Note:   For more information, see Xilinx Answer 71825.

 

A CLK_TX is generated based on the SD{0,1}_OTAPDLYSEL[5:0] register and multiplexed with the feedback clock for SD_CLK value > 33 MHz as the select line. If SD_CLK is greater than 25 MHz, the CLK_TX is selected as the transmission clock for the TX CMD/DATA delay. The CLK_TX is shifted by up to a fully divided clock cycle from CLK_0 in increments of 1/DIV. The TX clock delay can be calculated (This Equation) using the OTAP delay, the DLL divisor, and a clock period.

Equation 26-1      Delay = (OTAPDLYSEL[5:0] x Clock Period) x (1/DLL_DIV)

For example, calculate the TX clock delay with the following values.

OTAPDLYSEL[5:0] = 4

Clock period = 5 ns (1/DLL_REF_CLK)

DLL_DIV = 7.5

TX clock delay = (4 x 5) x (1/7.5) = 2.667 ns

A CLK_RX is generated based on the SD{0,1}_ITAPDLYSEL[7:0] register and multiplexed with the feedback clock for SD_CLK value ≥ 33 MHz as the select line. If SD_CLK is ≥ 33 MHz, the CLK_RX is selected as the receive clock for the RX clock delay unit.The CLK_RX is shifted by up to a fully divided clock cycle from CLK_0 in increments of 1/(4 x DIV). The RX clock delay is calculated (This Equation) using the ITAP delay, DLL divisor, and a clock period.

Equation 26-2      Delay = (ITAPDLYSEL[7:0] x Clock Period) x (1/4 x DLL_DIV)

For example, calculate the RX clock delay with the following values.

ITAPDLYSEL[7:0] = 4

Clock period = 5 ns (1/DLL_REF_CLK)

DLL_DIV = 7.5

RX clock delay = (4 x 5) x (1/(4 x 7.5)) = 0.667 ns