Receiver Data Capture

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The UART continuously over-samples the UARTx_RxD signal using UART_REF_CLK and the clock enable (baud_sample). When the samples detect a transition to a Low level, it can indicate the beginning of a start bit. When the UART senses a Low level at the UART_RxD input, it waits for a count of half of BDIV baud rate clock cycles, and then samples three more times. If all three bits still indicate a Low level, the receiver considers this to be a valid start bit, as illustrated in This Figure for the default BDIV of 15.

Figure 21-4:      Default BDIV Receiver Data Stream

X-Ref Target - Figure 21-4

X19866-receiver-data-stream.jpg

When a valid start bit is identified, the receiver baud rate clock enable (baud_rx_rate) is re-synchronized so that further sampling of the incoming UART RxD signal occurs around the theoretical mid-point of each bit, as illustrated in This Figure.

Figure 21-5:      Re-synchronized Receiver Data Stream

X-Ref Target - Figure 21-5

X19867-resynchronized-data-stream.jpg

When the re-synchronized baud_rx_rate is High, the last three sampled bits are compared. The logic value is determined by majority voting; two samples having the same value define the value of the data bit. When the value of a serial data bit has been determined, it is shifted to the receive shift register. When a complete character has been assembled, the contents of the register are then pushed to the RxFIFO.