Receiving Frames

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

When a frame is received with the receive circuits enabled, the controller checks the address and the frame is written to system memory in the following cases.

The destination address matches one of the four specific address registers. This is applicable for cases where the MAC address for the controller is set in the gem.spec_add{1:4}_bottom and gem.spec_add{1:4}_top registers.

The received frame's type/length field matches one of the four type ID registers. The available type ID registers are gem.spec_type{1:4}. This is applicable for cases where Ethernet type/length field based filtering is required.

Unicast or multicast hash is enabled through gem.network_config[unicast_hash_enable] or gem.network_config[multicast_hash_enable] register bits, then the received frame is accepted, only if the hash is matched.

The destination address is a broadcast address (0xFFFFFFFFFFFF) and broadcasts are allowed.

This option is set using the gem.network_config[no_broadcast] bit.

The controller is configured for promiscuous mode writing a 1 to the gem.network_config[copy_all_frames] bit.

A match is found in the I/O address filtering interface.

The register gem.receive_q{ , 1}_ptr points to the next entry in the receive buffer descriptor list and the controller uses this as the address in system memory to write the frame. When the frame is completely received and written to system memory, the controller then updates the receive buffer descriptor entry with the reason for the address match, marks the area as being owned by software, and sets the receive complete interrupt (gem.int_status[receive_complete] = 1). Software is then responsible for copying the data to the application area and releasing the buffer.

If the controller is unable to write the data at a rate to match the incoming frame, then the receiver overrun interrupt is set (gem.int_status[receive_overrun] = 1). If no receive buffer is available, (that is, the next buffer is still owned by software), a receive-buffer not available interrupt is set. If the frame is not successfully received, a statistic register is incremented and the frame is discarded without informing software.