Reference Clock

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The reference clock is generated in the PS clock subsystem. The input clock source can be selected based on the crl_apb.SDIO{0,1}_REF_CTRL[srcsel] bits, where the source can be from the RPLL, IOPLL, or DPLL. The crl_apb.SDIO{0,1}_REF_CTRL[divisor0] register selects the 6-bit programmable divider 0. The crl_apb.SDIO{0,1}_REF_CTRL[divisor1] register selects the 6-bit programmable divider 1.The crl_apb.SDIO{0,1}_REF_CTRL[clkact] bit selects whether the clock should be gated or enabled.