Register Access via APB Slave Interface

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The programming model for the PS and PL SYSMON units is described from a processor point of view with access to the PSSYSMON, PLSYSMON, and AMS register sets provided via a memory mapped LPD APB slave interface in the IOP. In this case, any processor connected to the AXI interconnect can potentially control the SYSMON, PMU, RPU, APU, DAP controller, and masters instantiated in the PL.

The AMS and PSSYSMON register sets are natively connected as an ABP slave interface and are protected by the XPPU protection unit. Check that the [jtag_locked] bit is “0” in the MON_STATUS register to make sure the clock is operating within the recommended range before attempting to access the PS SYSMON registers.

By contrast, the PL SYSMON unit's PLSYSMON register set has several programming interface paths that can be enabled and potentially at the same time. One of the default access paths is also to the memory mapped APB slave interface in the IOP. The other access paths to the PL SYSMON unit registers, including PL fabric and serial access, are described in Register Access via PL Fabric andSerial Channels.

The JTAG DAP controller can use the AXI interconnect to access the APB slave interfaces. For bandwidth considerations, the DAP controller via JTAG is a serial interface. The access paths to the PL unit are shown in This Figure. There are several conditions and restrictions that control access to all register sets.