Register Access via PL Fabric andSerial Channels

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

There are several options for accessing the PL SYSMON unit registers other than the APB slave interface in the IOP. See Table: PL SYSMON Unit Register Access Interfaces.

DRP slave interface (SYSMONE4 primitive instantiated)

I2C/PMBus interface (package pins and SYSMONE4 primitive instantiated)

PL TAP controller (debug environment, arbitrates, can be locked out by bitstream)

Table 9-7:      PL SYSMON Unit Register Access Interfaces

Interface to PL SYSMON Unit

PL is Not Configured

PL is Configured

No SYSMONE4

SYSMONE4 Instantiated

APB slave interface(1)

Yes, but VCCINT required and disabled PCAP isolation wall.

Yes, if [accessible] and not isolated.

No.(2)

DRP via PL fabric

Not applicable.

No.

Yes, if connected.

I2C/PMBus

Yes.

No.

Yes, if connected.

JTAG DAP controller

Yes.

Yes, unless disabled by bitstream.

Yes, unless disabled by bitstream.

Notes:

1.The I2C/PMBus and PL JTAG arbitrate for access. The software should not access the SYSMONs via the AXI/APB interconnect when the I2C/PMBus or JTAG interfaces are being used.

2.If the PS needs to communicate with the PL SYSMON unit when the SYSMONE4 primitive is instantiated, then the PL design must include an alternative path that interfaces to AXI PS-PL interface to the DRP interface on the instantiated SYSMONE4 primitive. Such a design would result in the PL SYSMON being treated as a user-specific hardware peripheral by the PS and the base address of the PL SYSMON registers would be within the PS-PL interface address space.

3.Refer to Answer Record 71067 to know when the APB to DRP path is to be used.