Register Set

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The register set implements the SD host controller specification (version 3.00). The host controller register set also implements the data port registers for the programmed I/O (PIO) mode transfers. The register set provides the control signals to the rest of the controller, monitors the status signals to set the interrupt status bits, and eventually generates interrupt signal.

The SD/SDIO controller registers are programmed by the processor through the AXI slave interface. Interrupts are generated to the host processor based on the values set in the interrupt status register and interrupt enable registers.

The registers are listed in Table: SD Controller Register Overview.