Register Sets

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

Table: Register Sets Overview summarizes the memory-mapped control and status registers for all three register sets AMS, PSSYSMON, and PLSYSMON. Register bit details are described in the Zynq UltraScale+ MPSoC Register Reference (UG1087) [Ref 4].

Software access to the registers is described in Register Access via APB Slave Interface. The register map for the PL SYSMON when accessed using JTAG, I2C/PMBus or the DRP is described in the UltraScale Architecture System Monitor User Guide (UG580) [Ref 6].

Table: Register Sets Overview includes the registers from the AMS, PSSYSMON (PS), and PLSYSMON (PL) register sets. The register base addresses are as follows.

AMS: 0xFFA5_0000

PS SYSMON: 0xFFA5_0800

PL SYSMON: 0xFFA5_0C00

Table 9-6:      Register Sets Overview

System Address

Register Name

AMS

PS

PL

Description

SYSMON, AMS Register Set

0xFFA5_0000

MISC_CTRL

1

 

 

Invalid register access and DRP access.

0xFFA5_0010

ISR_{0, 1}, IMR_{0, 1},
IER_{0, 1}, IDR_{0, 1}

8

 

 

Interrupt status and mask for alarms and APU register address decode errors to generate IRQ 88.

0xFFA5_0040

PS_SYSMON_CONTROL_STATUS

1

 

 

Control sequencer, reset,  conversion trigger.

0xFFA5_0044

PL_SYSMON_CONTROL_STATUS

1

 

 

Indicator for PS ability to access PL SYSMON registers via APB slave interface.

0xFFA5_0050

MON_STATUS (indicators).

1

 

 

Current channel, busy, and clock health.

0xFFA5_0060
0xFFA5_006C

VCC_PSPLL and VCC_PSBATT.

2

 

 

Measurement registers.

0xFFA5_0074 -
0xFFA5_0084

VCCBRAM, VCCINT, VCCAUX, VCC_PSDDR_PLL, and VCC_PSINTFP_DDR.

5

 

 

Measurement registers.

PS SYSMON Configuration Registers, PSSYSMON Register Set

0xFFA5_08FC

STATUS_FLAG

 

1

 

Alarm status and power indicator.

0xFFA5_0900

CONFIG_REG0

 

1

 

Single-read, averaging, and sampling modes.

0xFFA5_0904

CONFIG_REG1

 

1

 

PS alarm disables [0:6] and sequencer mode.

0xFFA5_0908

CONFIG_REG2

 

1

 

Sleep mode, ADC clock divider ratio.

0xFFA5_090C

CONFIG_REG3

 

1

 

PS alarms disables [8:13].

0xFFA5_0910

CONFIG_REG4

 

1

 

Low-rate channel skips, EOS select.

PL SYSMON Configuration Registers, PLSYSMON Register Set

0xFFA5_0CFC

STATUS_FLAG

 

 

1

Alarm status, power indicator, VREF selection, PL JTAG access indicators.

0xFFA5_0D00

CONFIG_REG0

 

 

1

Multiplexer, single-read channel, averaging and sampling modes.

0xFFA5_0D04

CONFIG_REG1

 

 

1

PL alarm disables [0:6] and sequencer mode.

0xFFA5_0D08

CONFIG_REG2

 

 

1

Sleep mode, ADC clock divider ratio.

0xFFA5_0D10

CONFIG_REG4

 

 

1

Low-rate channel skips, EOS select, and VUser voltage range select.

PS and PL Sequencer Configuration (PS SYSMON and PL SYSMON Registers)

0xFFA5_0xxx
{920, 918}
0xFFA5_0xxx
{D20, D24, D18}

PS: SEQ_CHANNEL{0, 2}
PL: SEQ_CHANNEL{0, 1, 2}

 

2

3

Select sensor channels for the normal sequence loop. Alternate name: SEQCHSEL.

0xFFA5_0xxx
{9E8, 9F0}
0xFFA5_0xxx
{DE8, DEC, DF0}

PS: SEQ_LOW_RATE_CHANNEL{0, 2}
PL: SEQ_LOW_RATE_CHANNEL{0, 1, 2}

 

2

3

Select sensor channels for the low-rate sequence loop. Alternate name: SLOWCHSEL.

0xFFA5_0xxx
{928, 91C}
0xFFA5_0xxx
{D28, D2C, D1C}

PS: SEQ_AVERAGE{0, 2}
PL: SEQ_AVERAGE{0, 1, 2}

 

2

3

Enable sensor channel measurement averaging. Alternate name: SEQAVG.

0xFFA5_0Dxx

PL: SEQ_INPUT_MODE{0, 1}

 

 

2

Select input sampling circuitry, unipolar, bipolar for external voltage nodes. Alternate name: SEQINMODE.

0xFFA5_0Dxx

PL: SEQ_ACQ{0, 1}

 

 

2

Select option to extend sampling time; potentially better reading. Alternate name: SEQACQ.

PS and PL ADC Results and Thresholds (PS SYSMON and PL SYSMON Registers)

(1)

Voltage Node Names.

 

~10

~10

Voltage measurements.

 

TEMP_{LPD, FPD, PL}

 

2

1

Temperature measurements.

 

MIN_xx, MAX_xx

 

24

22

Minimum, maximum voltage and temperature readings.

 

ALARM_UPPER_xx, ALARM_LOWER_xx

 

24

22

Upper, lower alarm thresholds.

Notes:

1.The address offsets and names for the measurement, temperature, minimum/maximum, and upper/lower threshold registers are shown in table Table: PS SYSMON Sensor Channels and Table: PL SYSMON Sensor Channels. Table: Measurement Registers in AMS Register Set shows the measurement registers for several basic channels measured by the PS SYSMON unit.