Relationship between DST-Q and STAD-Q

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

Software sets up DST-Q elements with predefined UserHandle values and points to empty buffers. For example, in This Figure a packet-0 spans across two DST-Q elements; one STAD-Q element is updated with the handle value of the last DST-Q element used by the packet and corresponding packet length. Software maintains the number of DST-Q elements used (buffers used and appropriate buffer fragment pointers) for a particular status completion.

The DMA provides programmable options for the following.

Number of status Qs: The DMA can be operated in 3-Q mode or 4-Q mode. In 3-Q mode, only a single status-Q is used for both the SRC and DST queues.

32-bit or 64-bit status Q: DMA provides an option to use the 32-bit status Q or 64-bit status Q. The upper 32 bits of the status Q are unavailable when the 32-bit status Q mode of operation is programmed.

Note:   In rare circumstances, the status-Q might not be updated with a completion status when an interrupt is received. These issues can be resolved by reading the DMA completion interrupt status register twice before reading the status-Q.