A requested power down occurs when the APU core power down is specifically requested through the REQ_PWRDWN_TRIG global registers. Setting a particular bit in the register would power down the APU. In this case, the PMU directly proceeds with powering down the APU Core. For REQ_PWRDWN_TRIG register description see the Zynq UltraScale+ MPSoC Register Reference (UG1087) [Ref 4].
Ensure that the appropriate bit position in the REQ_PWRDWN_STATUS global register is set to 0 to indicate that the power down request is served by the PMU.