Reset Reason Register

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The cause for each reset is stored in the crl_apb.RESET_REASON register. Table: Reset Reason Register summarizes the different values for the reset reason register.

Table 38-2:      Reset Reason Register

Bit Field

Bit

Description

external_por

0

External POR; the PS_POR_B reset signal pin was asserted.

internal_por

1

Internal POR. A system error triggered a POR reset.

pmu_sys_reset

2

Internal system reset. A system error triggered a system reset.

psonly_reset_req

3

PS-only reset. Write to PMU_GLOBAL.GLOBAL_RESET [PS_ONLY_RST].

srst

4

External system reset; the PS_SRST_B reset signal pin was asserted.

soft

5

Software system reset. Write to RESET_CTRL [soft_reset].

debug_sys

6

Software debugger reset. Write to BLOCKONLY_RST [debug_only].