Reset Services

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

This section describes the reset services. Various blocks can be reset through the REQ_SWRST_TRIG register if the interrupt for that specific reset is unmasked in the REQ_SWRST_INT_MASK register. The Table: Reset Requests lists the reset services.

Table 6-15:      Reset Requests

Reset Service Block

Request Bit

Description

PL

31

Resetting the PL domain depends on your design. This service is not handled by ROM code.

FPD

30

A hard reset of the full-power domain. Transactions are not flushed.

LPD

29

The PMU firmware uses this service to reset the low-power domain. This service is not handled by ROM code.

PS_ONLY

28

Acts as an internally generated a system reset (SRST). You can perform an isolation request on the PL prior to this event and then issue this request to only SRST the PS.

Reserved

27:26

Reserved

USB1

25

Cycles the reset for USB_1 by asserting the CRL_APB.RESET_LPD_TOP. USB1_CORERESET signal and then deasserting it.

USB0

24

Cycles the reset for USB_0 by asserting the CRL_APB.RESET_LPD_TOP.USB0_CORERESET signal and then deasserting it.

GEM3

23

Cycles the reset for GEM_3 by asserting the CRL_APB.RESET_IOU0.GEM3_RESET signal and then deasserting it.

GEM2

22

Cycles the reset for GEM_2 by asserting the CRL_APB.RESET_IOU0.GEM2_RESET signal and then deasserting it.

GEM1

21

Cycles the reset for GEM_1 by asserting the CRL_APB.RESET_IOU0.GEM1_RESET signal and then deasserting it.

GEM0

20

Cycles the reset for GEM_0 by asserting the CRL_APB.RESET_IOU0.GEM0_RESET signal and then deasserting it.

Reserved

19

Reserved

RPU

18

This service performs a sequence that resets the entire RPU and leaves the block in reset. You can request the R5_0 or R5_1 service to release the appropriate signal. The following resets signals are asserted:

PMU_GLOBAL_RESET_RPU_LS

CRL_APB.RESET_LPD_TOP.RPU_PGE_RESET

CRL_APB.RESET_LPD_TOP.R50_RESET

CRL_APB.RESET_LPD_TOP.R51_RESET

The following signals release the resets.

PMU_GLOBAL.RESET_RPU_LS

CRL_APB.RESET_LPD_TOP.PRPU_PGE_RESET

Prior to issuing an RPU request, the application should flush transactions to the RPU. The debug logic is not reset.

R5_1

17

Cycles the reset for the APU1 (R5_1) by asserting the CRL_APB.RESET_LPD_TOP.R51_RESET signal and then deasserting it.

R5_0

16

Cycles the reset for APU0 (R5_0) by asserting the CRL_APB.RESET_LPD_TOP.R51_RESET signal and then deasserting it.

Reserved

15:13

Reserved

Display_Port

12

Cycles the reset for the DisplayPort controller by asserting the CRL_APB.RESET_FPD_TOP.DP_RESET signal and then deasserting it.

Reserved

11

Reserved

SATA

10

Cycles the reset for the SATA controller by asserting the CRL_APB.RESET_FPD_TOP.SATA_RESET signal and then deasserting it.

PCIe

9

Cycles the reset for PCIe by asserting the CRL_APB.RESET_FPD_TOP.PCIE_RESET signal and then deasserting it.

GPU

8

This service performs a sequence that resets the entire GPU. Both pixel processors and the GPU resets are asserted and released by the following signals.

CRF_APB.RESET_FPD_TOP.GPU_RESET

CRF_APB.RESET_FPD_TOP.PP1_RESET

CRF_APB.RESET_FPD_TOP.PP0_RESET

PP1

7

Cycles the individual reset for the pixel processor by asserting the CRF_APB.RESET_FPD_TOP.GPU_PP1_RESET signal and the deasserting it.

PP0

6

Cycles the individual reset for the pixel processor by asserting the CRF_APB.RESET_FPD_TOP.GPU_PP0_RESET signal and the deasserting it.

Reserved

5

Reserved

APU

4

This service performs a sequence that resets the entire APU and L2 and leaves them in reset until the ACPU reset service (bits 3:0) are requested while cycling the reset on the L2 and surrounding APU logic. The debug logic is not reset. The following reset signals are asserted:

CRF_APB.RESET_FPD_APU.L2_RESET

CRF_APB.RESET_FPD_APU.ACPU3_RESET

CRF_APB.RESET_FPD_APU.ACPU2_RESET

CRF_APB.RESET_FPD_APU.ACPU1_RESET

CRF_APB.RESET_FPD_APU.ACPU0_RESET

The L2_RESET is released to make the L2 available.

ACPU3

3

Cycles the individual reset for the APU by asserting the CRF_APB.RESET_FPD_APU.ACPU3_RESET and the deasserting it.

ACPU2

2

Cycles the individual reset for the APU by asserting the CRF_APB.RESET_FPD_APU.ACPU2_RESET and the deasserting it.

ACPU1

1

Cycles the individual reset for the APU by asserting the CRF_APB.RESET_FPD_APU.ACPU1_RESET and the deasserting it.

ACPU0

0

Cycles the individual reset for the APU by asserting the CRF_APB.RESET_FPD_APU.ACPU0_RESET and the deasserting it.