Reset the Target Device (ONFI Reset)

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English
Table 25-4:      Reset Target Device Program Steps

Task

Register

Register Field

Register Offset

Bits

Value (Binary)

Enable transfer complete interrupt.

Interrupt_Status_Enable_Register

trans_comp_sts_en

0x014

2

1b'1

Program command register with reset command (0xFF), no ECC, and no DMA.

Command_Register

All

0x0C

31:0

0x0000FF00

TRAINING:   Select the device.

Memory_Address_Register2

Chip_Select

0x08

31:30

Targets chip select value.

Set reset.

Program_Register

Reset

0x10

8

1b'1

Poll for transfer complete event.

Interrupt_Status_Register

trans_comp_reg

0x1C

2

Wait until transfer is completed or wait time is over.

Clear the transmit complete interrupt after transfer completed.

Interrupt_Status_Enable_Register

trans_comp_sts_en

0x014

2

1b'0

Clear the transmit complete flag after transfer completed.

Interrupt_Status_Register

trans_comp_reg

0x1C

2

1b'1