Resetting the DLL

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English
Table 26-30:      Resetting the DLL

Task

Register

Register Field

Register Offset

Bits

Value

Disable clock.

reg_clockcontrol

clkctrl_sdclkena

0x2C

2

Clear bit 2

Set the DLL reset value.

SD_DLL_CTRL

SD{0,1}_DLL_RST

0x358

2 and 18

Set bit 2 and 18

Wait for 1 or 2 microseconds.

Release DLL from reset.

SD_DLL_CTRL

SD{0,1}_DLL_RST

0x358

2 and 18

Clear bit 2 and 18

Wait until internal clock to stabilize.

reg_clockcontrol

sdhcclkgen_intclkstable_dsync

0x2C

1

Read

Enable SD clock.

reg_clockcontrol

clkctrl_sdclkena

0x2C

2

Set bit 2