Retrigger

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

If the conventional descriptor update is used to feed the frame information to the DPDMA, then the DPDMA takes one or two clock cycles to process the new frame based on when the descriptor was updated by the software.

To solve this problem, DPDMA has a feature that allows the software to redirect or retrigger the DPDMA at any frame boundary.

DPDMA has a retrigger bit per channel that allows the software to redirect one or more channels. The flow of operations is as follows.

The software triggers the channel.

The channel waits for the first VSYNC to fetch the descriptor from the DSCR START ADDR register.

After the DPDMA channel is done processing the descriptor, it uses the NEXT ADDR (from the descriptor) to fetch the next descriptor.

The software can make the DPDMA channel loop on the same descriptor by giving the NEXT ADDR the same as the current descriptor address and setting an ignore done flag in the descriptor.

After the GPU is done rendering a new frame, the software comes and writes the start address, which points to the descriptor that holds a new frame and the software also writes the retrigger bit.

The DPDMA channel knows where the end of frame is (the descriptor flag that indicates the current descriptor is the last descriptor of the frame.) The DPDMA uses the start address to fetch the next descriptor if the software has provided a retrigger during the current frame. If the software has not provided a retrigger, the DPDMA channel fetches the next descriptor from the NEXT ADDR specified in the current descriptor.