Root Port Received Interrupt and Message Controller

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

A received interrupt and message controller collects interrupts and messages received from the PCIe hierarchy. Interrupt reception is applicable only to Root Port mode.

The following interrupt outputs are provided and connected to the AXI CPU (PS generic interrupt controller (GIC) in this case).

Two interrupt ports for MSI.

°Configurable address range, support for 64 vectors.

°Each interrupt output provides interrupt for 32 vectors.

One interrupt port for legacy interrupt.

One interrupt port for DMA.

One interrupt port for miscellaneous.

A 128-word deep message FIFO is implemented to hold messages and optionally MSI interrupts (based on msii_status_enable). Legacy interrupts, DMA channel interrupts, and optionally MSI are recorded into interrupt status registers. The FIFO level is indicated in the AXI_PCIE_MAIN.MSGF_RX_FIFO_LEVEL register. When this register is not zero, there are received interrupts or messages pending. The oldest received interrupt or message contents are available by reading the AXI_PCIE_MAIN.MSGF_RX_FIFO_TYPE, AXI_PCIE_MAIN.MSG, AXI_PCIE_MAIN.ADDRESS_LO, AXI_PCIE_MAIN.ADDRESS_HI, or AXI_PCIE_MAIN.DATA registers. When finished reading the current interrupt or message, the current element is removed from the FIFO by writing to the AXI_PCIE_MAIN.MSGF_RX_FIFO_POP register.

Each status register has a corresponding mask register; only when mask register bit entry = 1 and corresponding status register bit = 1, then an interrupt output is generated to the AXI CPU. For example, legacy interrupts provide AXI_PCIE_MAIN.MSGF_LEG_MASK and AXI_PCIE_MAIN.MSGF_LEG_STATUS registers. Only when MSGF_LEG_MASK[i] = 1 and MSGF_LEG_STATUS[i] = 1, is an interrupt output generated to the AXI-CPU. All four legacy interrupts are ORed together to generate one output interrupt.