SATA Clocking and Reset

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The AXI interface clock can be configured using the crf_apb.SATA_REF_CTRL register. For more details on AXI interface clocking, refer to PS Clock Subsystem.

The clocks used between the SATA host controller and PS-GTR transceiver are derived from the reference clock used in the serial input output unit (SIOU). For more details, refer to the PS-GTR Transceivers.

Follow these steps when generating the AXI interface clock for the SATA controller.

1.To avoid a performance impact when configuring for SATA generation 2 and generation 3, choose a frequency around 200 MHz (lower than 250 MHz).

2.For other configurations, choose a frequency near 100 MHz.

The block level reset to the SATA block is controlled by the crf_apb.RST_FPD_TOP[sata_reset] bit.