SD Command Generation

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The registers to generate SD commands are listed in Table: SD Commands.

Table 26-13:      SD Commands

Register

SDMA Command

ADMA2 Command

CPU Data Transfer

Non DAT Transfer

SDMA system address, argument 2

Yes/No

No/Auto CMD23

No/Auto CMD23

No/No

Block size

Yes

Yes

Yes

No (protected)

Block count

Yes

Yes

Yes

No (protected)

Argument 2

Yes

Yes

Yes

No (protected)

Transfer mode

Yes

Yes

Yes

No (protected)

Command

Yes

Yes

Yes

Yes

Table: SD Commands shows register settings for three transactions: SDMA generated transactions, ADMA2 generated transactions, and CPU data transfers and non-DAT transfers. When initiating transactions, the host driver programs these registers sequentially from 000h to 00Fh. The beginning register offset is calculated based on the type of transaction. The last written offset is always 00Fh because writing to the upper byte of the command register triggers the issuance of the SD command.