SD Configuration

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English
Table 26-14:      SD Configuration

Task

SD{0, 1}
Registers

Register Field

Register Offset

Bits

Value

Reset the controller.

reg_softwarereset

swreset_for_all

0x2f

0

1b'1

Wait until device has been reset.

reg_softwarereset

swreset_for_all

0x2f

0

Read operation

Read and save controller capabilities(1).

reg_capabilities

ALL

0x40

63:0

Read operation

Select voltage 3.3V and enable bus power.

reg_powercontrol

pwrctrl_sdbusvoltage | pwrctrl_sdbuspower

0x29

3:1,0

4b'1111

Change the clock frequency to 400 KHz (see Table: SD Clock Frequency Change).

Select 32-bit ADMA2 mode.

reg_hostcontrol1

hostctrl1_dmaselect

0x28

4:3

2b'10

Enable all interrupt status except card interrupt initially.

reg_normalintrstsena

ALL

0x34

15:0

0xFEFF

Enable error interrupts.

reg_errorintrstsena

ALL

0x36

12:0

Write 3FF h

Disable all interrupt signals.

reg_normalintrsigena

ALL

0x38

15:0

Write 0000h

Disable all error signals.

reg_errorintrsigena

ALL

0x40

12:0

Write 000h

Transfer mode register: default value.

DMA enabled, block count enabled, data direction card to host (read).

reg_transfermode

xfermode_dmaenable | xfermode_blkcntena

| xfermode_dataxferdir

0x0C

4, 1, and 0

Write 1 to all bits

Set block size to 512 by default.

reg_blocksize

xfer_blocksize

0x04

11:0

Write 200h

Notes:

1.the re-tuning interval in the SDIO capabilities register is determined by the IOU_SLCR.SD_CONFIG_REG3 [SD0_RETUNETMR] and [SD1_RETUNETMR] fields. The default value for this register is set to 0x8, which enables auto refresh at 128s. The software driver must ensure programming this register to the appropriate value based on your specific application requirements.

Table 26-15:      SD Clock Frequency Change

Task

SD{0, 1}
Registers

Register Field

Register Offset

Bits

Value

Disable clock.

reg_clockcontrol

clkctrl_intclkena and clkctrl_sdclkena

0x2C

2 and 0

Write 0

Set clock divisor

reg_clockcontrol

clkctrl_sdclkfreqsel and clkctrl_intclkena

0x2C

15:7 and 0

Write 1 to bit 0 and divisor value to bits 15:7.

Wait for 1 or 2 microseconds

Wait until internal clock stabilized.

reg_clockcontrol

sdhcclkgen_intclkstable_dsync

0x2C

1

Read until set

Enable SD clock.

reg_clockcontrol

clkctrl_sdclkena

0x2C

2

Write 1

Notes:

1.The internal clock enable signal (clkctrl_intclkena) needs to cleared for at least one SD_CLK cycle whenever clock frequency is changed.