The [SD0_ITAPCHGWIN] and [SD1_ITAPCHGWIN] bits in the IOU_SLCR.SD_ITAPDLY register are used to gate the output of the tap delay lines to avoid glitches being propagated into the controller. This signal should be asserted a few clocks before the corectrl_itapdlysel changes and stay asserted for a few clocks afterwards.
For SDIO{0, 1}, use the IOU_SLCR register set and the tap delay values in Table: SD104/eMMC200 Mode through Table: eMMC HSD Mode.
Register Bit |
SDIO0 Bank 0 |
SDIO{0, 1} |
SDIO{0, 1} Bank 2 |
Description |
---|---|---|---|---|
SD_ITAPDLY[SDx_ITAPDLYENA] |
1'b1 |
1'b1 |
1'b1 |
SLCR I tap delay enable (RX). |
SD_ITAPDLY[SDx_ITAPDLYSEL] |
N/A(1) |
N/A(1) |
N/A(1) |
RX tap delay values. |
SD_OTAPDLY[SDx_OTAPDLYSEL] |
6'b000011 |
6'b000011 |
6'b000010 |
TX tap delay values. |
Notes: 1.The (N/A) value is calculated from auto-tuning by the SDIO controller. You can program this value with trial and error. |
Register Bit |
SDIO0 Bank 0 |
SDIO{0, 1} Bank 1 |
SDIO{0, 1} |
Description |
---|---|---|---|---|
SD_ITAPDLY[SDx_ITAPDLYENA] |
1'b1 |
1'b1 |
1'b1 |
SLCR I tap delay enable (RX). |
SD_ITAPDLY[SDx_ITAPDLYSEL] |
8'b00010100 |
8'b00010100 |
8'b00010100 |
RX tap delay values. |
SD_OTAPDLY[SDx_OTAPDLYSEL] |
6'b000011 |
6'b000011 |
6'b000011 |
TX tap delay values. |