SD Write Polled

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English
Table 26-21:      SD Write Polled

Task

SD{0, 1}
Registers

Register Field

Register Offset

Bits

Value

Check the present state register to make sure the card is present.

reg_presentstate

sdhccarddet_inserted_dsync

0x24

16

Read

If not already set, set block size to 512 (see Table: SD Set Block Size).

Set up ADMA2 (see Table: Setup ADMA2 Descriptor Table).

Set up mode register with auto CMD12 enable, block count enable, data transfer direction, DMA enable, and multi/single block select.

reg_transfermode

ALL

0x0C

5:0

0x37

Send block read command (CMD18) (see Table: SD CMD Transfer)

Check for transfer completed.

reg_normalintrsts

reg_errorintrsts

0x30

15

Read operation

Clear the interrupts (if any).

reg_normalintrsts

ALL

0x30

15:0

0xF3FF

Check transfer complete and clear if transfer is completed.

reg_normalintrsts

normalintrsts_xfercomplete

0x30

1

1b'1