The DDRC is responsible for mapping system addresses used by the PS and PL AXI masters to the SDRAM row, bank, and column addresses. Optimizing the mapping to specific data access patterns allows increased SDRAM utilization by reducing page and row change overhead. Many combinations of address remapping are not available however, the bank-row-column and row-bank-column configurations are achievable.
The first part of the mapping is the conversion of a system address to an AXI byte address. The DDRC maps the disjointed address regions into internal consecutive addresses. The second part of this mapping is conversion of AXI byte address to HIF word address. This is performed in the XPI block. The last part is the conversion of the HIF word address to the SDRAM address. A flexible address mapper maps the HIF word address to the SDRAM rank/bank/bank group/row/column address. This address mapper is located within the DDRC.
The address mapper maps HIF word addresses to SDRAM addresses by selecting the HIF address bit that maps to every applicable SDRAM address bit. The available address space is only accessible when no two SDRAM address bits are determined by the same HIF address bit. The registers ADDRMAPx (x = 0 to 11) are used to program the address mapper.
Each SDRAM address bit has an associated register vector to determine its source. The associated HIF address bit is determined by adding the internal base of the ADDRMAPx (x = 0 to 11) register to the programmed value for that register, as described in This Equation.
For example, an ADDRMAP3.addrmap_col_b7 register internal base is 7. When a full data bus is in use, column bit 7 is determined by This Equation.
If the ADDRMAP3.addrmap_col_b7 register is programmed to 2, then the HIF address bit is as shown in This Equation.
The result is that the column address bit 7 that is sent to the SDRAM is mapped to an HIF address bit of *_ADDR.
In the half bus-width mode, all the column bits shift up by one bit. In this case, the ADDRMAP3.addrmap_col_b6 register determines the mapping of the SDRAM column address bit 7. In the quarter bus-width mode (only supported for DDRA), all of the column bits shift up by two bits.