SGMII, 1000BASE-SX, or 1000BASE-LX

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The physical coding sublayer (PCS) can be configured to operate in SGMII, 1000BASE-SX, or 1000BASE-LX mode (1 Gb/s only). This allows the GEM to be used as a building block to support SGMII, 1000BASE-SX, or 1000BASE-LX as an interface to an external PHY, further reducing the pin count.

When bit [27] (SGMII mode) in the network configuration register (GEM{0:3}.network_config[sgmii_mode_enable]) is set, it changes the behavior of the auto-negotiation advertisement and link partner ability registers to meet the requirements of SGMII. Additionally, the time duration of the link timer is reduced from 10 ms to 1.6 ms.

Auto-negotiation is something that occurs between PHYs. SGMII is a MAC-PHY interconnect and the auto-negotiation functionality (defined in Clause 37 of IEEE Std 802.3) is used to transfer status information from the PHY to the MAC rather than to perform auto-negotiation. In SGMII mode, bits [11:10] of the link partner ability register return the data transfer rate of the link, which is previously negotiated by the PHY with its link partner PHY. The line rate is 1 Gb/s as SGMII hardwired to function at 1 Gb/s only. However, the data transfer rate can be forced down to 100 Mb/s or 10 Mb/s if the link partner is not capable. The 1000BASE-SX/LX only works at 1 Gb/s (both the data transfer rate and line rate). This information is used by configuration software to set bits [10] and [0] of the network configuration register.

The MAC transmit and receive data paths are reconfigured by the network configuration register bits [10, gigabit_mode_enable] and [11, pcs_select] for different modes and speeds of operation.

Note:   When using the PS-GTR, the configuration remains the same for 1000BaseX or SGMII i.e., the external PHY will have to be configured for the required mode. However, in 1000BaseX mode, only a fixed speed of 1G can be used.