SHA-3/384

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The SHA hardware accelerator included in the Zynq UltraScale+ MPSoC implements the SHA-3 algorithm and produces a 384-bit digest. It is used together with the RSA accelerator to provide image authentication. It is also used to perform an integrity check of the CSU and PMU ROMs prior to execution. The SHA-3 block generates a 384-bit digest value. If a design requires a 256-bit digest, use the least significant 256 bits of the digest (see Recommendation for Applications Using Approved Hash Algorithms NIST Special Publication 800-107 [Ref 56]).

The hash function is calculated on blocks that are 832-bits long (104 bytes). Only whole blocks can be processed through the SHA. All messages processed by the SHA-3 accelerator must be appropriately padded. See SHA-3 Standard: Permutation-Based Hash and Extendable-Output Functions, NIST FIPS PUB 202 [Ref 57] for padding requirements. SHA3-384 padding should be M || 01 || 10 * 1.