SMMU Architecture

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The SMMU performs address translation of an incoming AXI address and AXI ID (mapped to context) to an outgoing address (PA). The Arm SMMU architecture also supports the concept of translation regimes, in which a required memory access might require two stages of address translation. The SMMU supports the following.

Aarch32 short (32-bit) descriptor. Supports up to a 32-bit VA and 32-bit PA.

Aarch32 long (64-bit) descriptor. Supports up to a 32-bit VA and 40-bit PA.

Aarch64 (64-bit) descriptor. Supports up to a 49-bit VA and 48-bit PA.