SMMU Clocks and Resets

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The SMMU AXI interfaces are clocked by the TOPSW_MAIN_CLK clock in the AXI interconnect for the FPD. The clock generator is described in PS Clock Subsystem. The SMMU reset is in the FPD reset domain.