The SPI controller operates in three modes:
In multi-master mode, the controller’s output signals are 3-stated when the controller is not active and can detect contention errors when enabled. The outputs are 3-stated immediately by resetting the SPI enable bit. An interrupt status register indicates a mode fault.
In slave mode, the controller receives the serial clock from the master device and uses the SPI_REF_CLK to synchronize data capture. The slave mode includes a programmable start detection mechanism when the controller is enabled while the slave select (SS) signal is asserted. The read and write FIFOs provide buffering between the SPI I/O interface and the software servicing the controller via the APB slave interface. The FIFOs are used for both slave and master I/O modes.