SWDT Functional Description

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The control logic block has an APB interface connected to the system interconnect. Writes to the MODE and CONTROL registers require a key. The mode register requires the zKEY and the controller register requires the cKEY.

The zero mode register controls the behavior of the watchdog timer when its internal 24-bit counter reaches zero. Upon receiving a zero signal, the control logic block (if both mode bits [WDEN] and [IRQEN] are set) asserts the interrupt output signal for MODE IRQLN clock cycles, and (if [WDEN] is set) also asserts the reset output signals for approximately one clock cycle. The 24-bit counter then stays at zero until it is restarted.

The counter control register sets the timeout period by setting reload values in CONTROL[CLKSET] and [CRV] bits to control the prescaler and the 24-bit counter.

The restart register is used to restart the counting process. Writing to this register with a matched key causes the prescaler and the 24-bit counter to reload the values from the CRV signals.

The status register shows whether the 24-bit counter reaches zero. Regardless of the [WDEN] bit in the zero mode register, the 24-bit counter keeps counting down to zero when it is not zero and the selected clock source is present. Once the 24-bit counter reaches zero, the [WDZ] bit of the status register is set and remains set until the 24-bit counter is restarted.

The prescaler block divides down the selected clock input. The [CLKSEL] bit is sampled at every rising clock edge.

The internal 24-bit counter counts down to zero and stays at zero until it is restarted. While the counter is at zero, the zero output signal is High.