Sampler and Realign

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

There are four samplers that operate on four phases of a half-rate clock. Because the four phases are quadrature phases, they are collectively called the IQ path. The sampling clock is the recovered clock that is the output of the IQ-phase interpolator (PI). The samplers operate on a full CMOS-level clock, sample the low-swing data received from the equalizer, and output CMOS-level data. Local current-mode logic (CML) to CMOS converters convert the recovered clock phases coming from the PI in CML levels to CMOS levels for sampling.

The outputs of the four samplers are finally realigned to one phase of the recovered clock, inside the realign block, before being sent to the digital loop filter. The on-chip EyeScan, that measures the horizontal eye opening known as an E-sampler, operates at half the rate of clocks coming from the EyeScan PI. For the vertical EyeScan (opening), the EyeScan digital-to-analog converter (DAC) is used to control the sampling point in E-samplers in the Y-direction. Sampler offsets are independently calibrated out for these samplers using an offset calibration scheme.