Secure Stream Switch

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The secure-stream switch (SSS) allows data movement between multiple sources and destinations. During boot, the secure-stream switch is exclusively controlled by the CSU. After boot, any system master can control the configuration of the secure-stream switch. Table: Secure Stream Switch lists the possible connections in the secure stream switch.

The JTAG PS TAP controller is accessible via the dedicated PS pins. The AXI DMA is in the CSU.

Table 11-6:      Secure Stream Switch

 

Destinations

AXI DMA

JTAG

AES-GCM

PCAP

SHA

Sources

AXI DMA

X

 

X

X

X

JTAG

X

 

 

X

 

AES-GCM

X

 

 

X

 

PCAP

X

X

 

 

 

ROM

 

 

 

 

X

The secure-stream switch is configured using a single SSS configuration register (csu_sss_cfg). Some common configurations for the secure stream switch are listed in Table: Secure Stream Switch Configurations.

Table 11-7:      Secure Stream Switch Configurations

Secure Stream Switch Setup

Description

CSU_SSS_CFG Setting

DMA to DMA

DMA loopback.

0x00000050

DMA to PCAP

PL configuration.

0x00000005

DMA to AES, AES to DMA

Secure PS configuration.

0x000005A0

DMA to AES, AES to PCAP

Secure PL configuration.

0x0000050A

DMA to DMA, DMA to SHA

PS image load with simultaneous SHA calculation.

0x00005050