Sequence for Enabling DMA Channel

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The following DMA channel enable sequence is recommended. The process can be completed in any order, provided the DMA enable value is set to 1 in the end.

Note:   Prior to enabling the DMA channel, the source scatter-gather queue, the destination scatter-gather queue, the DMA source completion status queue, and the DMA destination completion status queue must be initialized.

1.Verify that the DMA channel is idle.

Read the DMA running and verify it reads 0x0. If a non-0, follow the instructions provided in Disabling an Active DMA Channel.

2.Initialize the queue base address and attributes.

a.Write SRC_Q_PTR_LO and SRC_Q_PTR_HI with the base address of the queue.

b.Write DST_Q_PTR_LO and DST_Q_PTR_HI with the base address of the queue.

c.Write STAS_Q_PTR_LO and STAS_Q_PTR_HI with the base address of the queue.

d.Write STAD_Q_PTR_LO and STAD_Q_PTR_HI with the base address of the queue.

3.Initialize the queue size.

a.Write SRC_Q_SIZE to the size of the queue.

b.Write DST_Q_SIZE to the size of the queue.

c.Write STAS_Q_SIZE to the size of the queue.

d.Write STAD_Q_SIZE to the size of the queue.

4.Initialize queue Next pointers to the beginning of the queue.

a.Write SRC_Q_NEXT = 0x0.

b.Write DST_Q_NEXT = 0x0.

c.Write STAS_Q_NEXT = 0x0.

d.Write STAD_Q_NEXT = 0x0.

5.Initialize scatter-gather queues to the empty condition (no DMA operations to execute).

a.Write SRC_Q_LIMIT = 0x0.

b.Write DST_Q_LIMIT = 0x0.

6.Initialize status queues to the fully available condition (all status queue elements except one, which is needed to preserve software flow control, are available).

a.STAS_Q_LIMIT set to (STAS_Q_SIZE-1).

b.STAD_Q_LIMIT set to (STAD_Q_SIZE-1).

7.Initialize all STAS and STAD queue elements to 0x0.

DMA completion status queue elements must be initialized to 0x0 so that the software can specify the completion of status elements. Status elements return a non-0 value when complete.

8.Optionally, initialize all the SRC and DST scatter-gather queue elements.

The initialization of source and destination SGL elements is solely at the discretion of software. Source and destination SGL elements will not be fetched until they have been filled in with DMA transaction instructions and the associated queue's LIMIT pointer advanced to give these elements to the DMA channel to execute.

9.Write DMA enable = 1 to enable the DMA channel.

Optionally, for interrupt mode, the following registers are programmed to enable the interrupts.

AXIPCIE_DMA.DMA_CHANNEL_PCIE_INTERRUPT_CONTROL for enabling interrupts in the PCIe domain.

AXIPCIE_DMA.DMA_CHANNEL_AXI_INTERRUPT_CONTROL for enabling interrupts in the AXI domain.

Interrupts for various events can be enabled, SGL completion (EOP) or error. Additionally, coalesce count can be set to control the frequency of interrupt generation.

 

IMPORTANT:   DMA channel MSI-X and MSI interrupts are signaled using the MSI-X/MSI interrupt vector corresponding to their DMA channel number. For example, DMA channel[0] interrupts are signaled on MSI-X/MSI vector 0, DMA channel[1] interrupts are signaled on MSI-X/MSI vector 1, etc.