Slave Mode SCLK

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

In slave mode, the controller samples the MOSI and SS I/O signals and drives the MISO signal using the SCLK from the attached master. The input signals are synchronized to the SPI_REF_CLK and processed by the controller.

Note:   The SPI_REF_CLK frequency should be at least 2x the SCLK frequency for the controller to properly detect the start of the word transfer on the SPI bus.