Snoop Control Unit

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The integrated snoop-control unit (SCU) connects the APU MPCore and an accelerator coherency port (ACP) used in Zynq UltraScale+ MPSoCs. The SCU also has duplicate copies of the L1 data-cache tags for coherency support. The SCU is clocked synchronously and at the same frequency as the processors.

The SCU contains buffers that can handle direct cache-to-cache transfers between processors without having to read or write any data to the external memory system. Cache-line migration enables dirty-cache lines to be moved between processors, and there is no requirement to write back transferred cache-line data to the external memory system. The Cortex-A53 MPCore processor uses the MOESI protocol to maintain data coherency between multiple cores.