1.Place the PHY into reset. The PS-GTR reset bit in the PHY_reset [bit 1 of DP_PHY_RESET] bit should be set to 1.
DP_PHY_RESET = 0x01
2.Disable the transmitter.
DP_TRANSMITTER_ENABLE = 0x00
3.Set the clock divider by programming the dp.DP_AUX_CLOCK_DIVIDER[clk_div] register.
4.Set DisplayPort clock speed. Program the dp.DP_PHY_CLOCK_SELECT[sel] register with the desired link speed.
5.Bring the PHY out of reset. Write 0 to the DP.DP_PHY_RESET [GT_RESET] bit.
dp.DP_PHY_RESET = 0x00
6.Wait for the PHY reset done and PLL lock.
DP_PHY_STATUS bits [1:0] = 2'b11 and DP_PHY_STATUS bit  = 1'b1
7.Enable the transmitter.
DP_TRANSMITTER_ENABLE = 0x01
8.(Optional) Turn on the interrupt mask for the HPD.
INTERRUPT_MASK = 0x00
Note: At this point, the source controller is initialized and ready to use. The link policy maker should be monitoring the status of HPD and taking appropriate action for connect/disconnect events or HPD interrupt pulses.
Although #DP_PHY_RESET has two bits (GT_RESET and PLL_RESET), use GT_RESET during source controller setup.