Source Controller Setup

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

1.Place the PHY into reset. The PS-GTR reset bit in the PHY_reset [bit 1 of DP_PHY_RESET] bit should be set to 1.

DP_PHY_RESET = 0x01

2.Disable the transmitter.

DP_TRANSMITTER_ENABLE = 0x00

3.Set the clock divider by programming the dp.DP_AUX_CLOCK_DIVIDER[clk_div] register.

4.Set DisplayPort clock speed. Program the dp.DP_PHY_CLOCK_SELECT[sel] register with the desired link speed.

5.Bring the PHY out of reset. Write 0 to the DP.DP_PHY_RESET [GT_RESET] bit.

dp.DP_PHY_RESET = 0x00

6.Wait for the PHY reset done and PLL lock.

DP_PHY_STATUS bits [1:0] = 2'b11 and DP_PHY_STATUS bit [4] = 1'b1

7.Enable the transmitter.

DP_TRANSMITTER_ENABLE = 0x01

8.(Optional) Turn on the interrupt mask for the HPD.

INTERRUPT_MASK = 0x00

Table 33-15:      Source Controller Setup and Initialization

Task

DP Register Set

Bit Field

Register Offset

Bits

Value

Reset PHY.

DP_PHY_RESET

GT_RESET

0x200

1

1

Disable transmitter.

DP_TRANSMITTER_ENABLE

TX_EN

0x0080

0

1b'0

Set the clock divider.

DP_AUX_CLOCK_DIVIDER

AUX_SIGNAL_WIDTH_FILTER | CLK_DIV

0x010C

15:0

Refer to the register for the value.

Set DisplayPort clock.

DP_PHY_CLOCK_SELECT

SEL

0x0234

2:0

0x05 = 5.40 Gb/s link

0x03 = 2.70 Gb/s link

0x01 = 1.62 Gb/s link

Bring the PHY out of reset.

DP_PHY_RESET

GT_RESET

0x200

1

1'b0

Wait for reset done by checking DP_PHY_STATUS register.

Check reset done.

DP_PHY_STATUS

RESET_LANES_0_1

0x0280

1:0

2b'11 indicates reset done for lane 0 and lane 1.

Check PLL locked.

DP_PHY_STATUS

RESET_LANES_0_1

0x0280

4

1b'1 indicates PLL is locked.

Enable transmitter.

DP_TRANSMITTER_ENABLE

TX_EN

0x0080

0

1b'1

Note:   At this point, the source controller is initialized and ready to use. The link policy maker should be monitoring the status of HPD and taking appropriate action for connect/disconnect events or HPD interrupt pulses.

Although #DP_PHY_RESET has two bits (GT_RESET and PLL_RESET), use GT_RESET during source controller setup.