Staged Response to a Tamper Event

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

Systems might require multiple responses to a tamper event. The csu_tamper_trig register, combined with the csu_tamper_0 register, provides a way to have a two-staged response to a tamper event. An example of building a staged response is as follows.

1.Set bit 0 in csu_tamper_6 (i.e., generate an IRQ when VCCINT_LPD is out of range).

2.Set bit 2 in csu_tamper_0 (i.e., enter secure lockdown).

3.Tamper event occurs. VCCINT_LPD goes out of range.

4.The csu_tamper_6 causes an IRQ to be set.

5.User software responds to IRQ and clears the tamper.

6.User software performs some additional action, such as logging or zeroing of configuration or data.

7.User software writes to csu_tamper_trig register.

8.Csu_tamper_0 response is executed. The device goes into secure lockdown.

The tamper events can be securely and permanently logged for later analysis. Logging can be done within the device through a user eFUSE.