Step 2:

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

a.Ensure the POINT_TYPE bit in ZDMA_CH_CTRL0 is set to 1.

b.Allocate the source buffer descriptor objects in memory. Ensure that the buffer descriptor object address is 256-bit aligned. In case any buffer descriptors are not allocated as cache coherent or the buffer descriptors are not flushed prior to enabling DMA channel, set the AXCOHRNT field to 1. The address of the first buffer descriptor in a list is written to ZDMA_CH_SRC_START_LSB and ZDMA_CH_SRC_START_MSB.

c.Allocate the destination buffer descriptor objects in memory. Ensure that the buffer descriptor object address is 256-bit aligned. In case any buffer descriptors are not allocated as cache coherent or the buffer descriptors are not flushed prior to enabling the DMA channel, set the AXCOHRNT field to 1. The address of the first buffer descriptor in a list is written to ZDMA_CH_DST_START_LSB and ZDMA_CH_DST_START_MSB. The AXCOHRNT bit is valid only in case of LPD DMA. The FPD DMA does not support coherency at buffer descriptor or buffer level.

 

TIP:   The buffer descriptors can also be pre-allocated during initialization time.