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Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

Upon transfer completion, the DMA channel provides interrupt(s) to the processor depending upon how the INTR field of the buffer descriptor(s) are set. For for information on handling interrupts, refer to Interrupt Handling.

Software can use ZDMA_CH_IRQ_DST_ACCT and/or ZDMA_CH_IRQ_SRC_ACCT to decipher the number of processed buffer descriptors on the source and destination sides. Software can internally maintain counters of both the number of source and destination buffer descriptors configured for the data transfer. Upon updating of the ZDMA_CH_IRQ_DST_ACCT and/or ZDMA_CH_IRQ_SRC_ACCT with an equal count, software can infer that the data transfer is complete. Software should count only those descriptors for which interrupts are enabled.