The store buffer (STB) holds store operations when they have left the load/store pipeline and are committed by the DPU. The STB can request access to the cache RAMs in the DCU, request the BIU to initiate linefills, or request the BIU to write the data out on the external write channel. External data writes are through the SCU. The STB can merge the following.
•Several store transactions into a single transaction if they are to the same 128-bit aligned address.
•Multiple writes into an AXI or CHI write burst. The STB is also used to queue maintenance operations before they are broadcast to other cores in the Cortex-A53 MPCore CPU cluster.
The Cortex-A53 MPCore L1 memory system consists of separate L1 instruction and data caches. It also consists of two levels of TLBs.
•Separate micro TLBs for both instruction and data sides.
•Unified main TLB that handles misses from micro TLBs.