Suffice DMA Descriptors

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

This section provides the details of the DMA descriptors. The scatter-gather queues supported by DMA are listed.

SRC-Q provides data buffer source information and corresponding STAS-Q to indicate completion of SRC-Q processing by the DMA

DST-Q provides destination buffer information and corresponding STAD-Q which indicates DST-Q processing completion by DMA

Source and destination scatter-gather queues describe the fragmentation of the source and the destination memory. The queues are independent. The DMA channel merges the information from the queues to perform DMA operations based on the fragmentation of each queue.

The Q elements layout is shown in This Figure.

Figure 30-7:      DMA SGL-Q Format

X-Ref Target - Figure 30-7

X15491-dma-sgl-q-register.jpg

The source and destination scatter-gather Q elements are 128 bits wide. The corresponding status scatter-gather Q elements can be chosen to be either 32-bit or 64-bit.

The description of various format fields are listed in Table: SRC-Q Element Descriptions, Table: DST-Q Element Descriptions, and Table: Status Q Element Descriptions.

Table 30-7:      SRC-Q Element Descriptions

Field Name

Location

Description

Source address

[63:0]

Source address.

Byte count

[87:64]

Byte count, a value of 0 implies 224 bytes.

Flags[7:0]

[95:88]

[7:4] DMA data read attribute

If source is AXI m_arcache[3:0] = [7:4]

If source is PCIe, PCIe attr[2:0] = [6:4]

[3] Reserved

[2] Interrupt

A value of 1, generates an interrupt when the status-Q is written with a DMA completion status and valid when EOP = 1. The interrupt is generated in either PCIe or AXI or both directions based on the DMA channel interrupt register configuration.

A value of 0, does not generate an interrupt.

[1] EOP

A value of 1, end of packet, status Q is updated when EOP is transferred to DMA destination.

A value of 0, not end of packet, packet can span multiple Q elements.

[0] Location

A value of 1, DMA data source is AXI

A value of 0, DMA data source is PCIe

UserHandle[15:0]

[111:96]

The UserHandle is copied from SRC SGL with EOP = 1 to corresponding STAS-Q elements in the UserHandle field.

It provides a means to associate SRC-Q to STAS-Q elements.

UserID[15:0]

[127:112]

UserID is copied from SRC SGL with EOP = 1 to corresponding STAS and STAD-Q element's UserID field.

It provides a means to transfer user specific data from source to destination.

Table 30-8:      DST-Q Element Descriptions

Field Name

Location

Description

Destination address

[63:0]

Destination address.

Byte count

[87:64]

Byte count.

Value of 0 implies 224 bytes.

Flags[7:0]

[95:88]

[7:4] DMA data write attribute.

If destination is AXI m_awcache[3:0] = [7:4].

If destination is PCIe, PCIe Attr[2:0] = [6:4].

[3:2] Reserved

[1] Enable one packet per destination SGL.

A value of 1, skip to next destination SGL on EOP.

A value of 0, pack packets back-to-back in destination SGL.

[0] Location

A value of 1, DMA data destination is AXI.

A value of 0, DMA data destination is PCIe.

UserHandle[15:0]

[111:96]

UserHandle is copied from the final DST SGL element used in packet transfer to corresponding STAD-Q element’s UserHandle field.

It provides a means to associate DST-Q elements to STAD-Q elements.

Reserved

[127:112]

Reserved

Table 30-9:      Status Q Element Descriptions

Field Name

Location

Description

UserID[15:0]

[63:48]

UserID copied from SRC SGL element with EOP=1

UserHandle[15:0]

[47:32]

For STAS-Q, this is copied from the SRC-Q element with EOP = 1.

For STAD-Q, this is copied from final DST-Q element used for packet transfer.

This provides software with a means to associate SRC/DST-Q with STAS/STAD elements.

Upper status is non-zero

[31]

For 64-bit status elements this bit is 1 when [63:32] = 0.

For 32-bit status elements, this bit always reads 0.

Completed byte count

[30:4]

Completed byte count.

Range is 0 to (227–1).

Internal error

[3]

Internal error during DMA operation.

Destination error

[2]

Destination error during DMA operation.

Source error

[1]

Source error during DMA operation.

Completed

[0]

Status Q element completion indication.

 

IMPORTANT:   Both UserHandle and UserID cannot be zero at the same time when using 64-bit status queues and checking the “upper status is non-zero” bit for a status queue update by the DMA. When not using the UserID field, keep the UserID to a fixed non-zero signature value so that the UserHandle can start from the value of zero.

Status-Q elements contain information for a single packet transfer. The upper status is a non-zero bit that provides a method to ensure that CPUs read the correct information in case of 32-bit atomic operations.

DMA errors are indicated in status-Q elements for packets that are able to be completed. In error situations where packets cannot complete, DMA errors are indicated in channel's error status registers.

These Qs can be resident either in host memory or AXI memory. Q elements are required to be in contiguous location for DMA to fetch multiple SRC/DST-Q elements in a burst fetch. The software driver sets up the Q elements in contiguous location and DMA takes care of wrap-around of Q. Every DMA channel has the following registers pertaining to each Q.

Q_PTR: Indicates the starting address of the Q.

Q_SIZE: The number of SGL elements in Q.

Q_LIMIT: An index of the first element still owned by the software; DMA hardware wraps around to start element location when Q_LIMIT is equal to Q_SIZE.

This Figure shows a DMA SGL-Q operation.

Figure 30-8:      DMA SGL-Q Operation Summary

X-Ref Target - Figure 30-8

X15492-dma-sql-q-operation.jpg