Based on the required address size, a page translation table walk can use fewer steps. For example, a 40-bit address translation (to 4 KB pages) takes four table-walker steps. A 36-bit address translation takes three table-walker steps. Thus, in a 40-bit address size system, performance is optimized by limiting the address size to 36 bits, if a 36-bit address size is sufficient for the application.
The interconnect addresses between various processing system (PS) masters to the translation buffer units (TBUs) of the system memory management unit (SMMU) are virtual addresses. The address bus (from master to SMMU) is 48 bits for the 64-bit compliant PS masters (APU, PCIe, SATA, DisplayPort, USB, GEM, SD, NAND, QSPI, and the CSU, LPD, and DMA units). The 32-bit PS masters provide a 32-bit address bus, which is zero-extended to 48 bits. The SMMU supports a 49-bit address. For PS-masters, the 49th address bit to the SMMU is zero, and the address bus from the programmable logic (PL) AXI interfaces into the PS is 49 bits.
The global system address map is shown in This Figure.
The SMMU supports two stage translations: Stage 1 (virtual address (VA) to intermediate physical address (IPA)), and stage 2 (IPA to physical address). The PS master virtualization target is primarily a stage 2 translation (for example, a hypervisor scenario uses only stage 2 translations). The PL can use a stage 1 and/or a stage 2 translation. For details on SMMU translation, see the SMMU Architecture section in Chapter 3.
For the stage 2 translation, the Arm v8 architecture supports a maximum of 48 bits of IPA address. For the stage 1 translation, the Arm v8 architecture supports a 49-bit maximum addressing.