System Interrupts

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

System interrupts can be generated when the controller for PCIe is used either as a Root Port or as an Endpoint. The five PCIe system interrupts (MSI0, MSI1, INT{A, B, C, D}, DMA, and MSC) are listed in Table: System Interrupts.

As an Endpoint, the following interrupts can be generated to the system controller.

DMA interrupts due to completion or an error when enabled; these are generated when the DMA operation is enabled.

Since the PCIe protocol does not support interrupts downstream, the host software can create an interrupt in the AXI domain.

Host software controlled interrupts provided per DMA channel which can be used for handshake purpose. Note that PCIe protocol doesn’t support interrupts downstream so this provides a means of host (Root Port) interrupting processor on MPSoC Endpoint. The interrupts are asserted by writing to the AXIPCIE_DMA*.DMA_CHANNEL_AXI_INTERRUPT_ASSERT [axi_software_interrupt] register.

All interrupts require an enabled AXIPCIE_DMA*.DMA_CHANNEL_AXI_INTERRUPT_CONTROL [interrupt_enable] bit. Additionally, for AXI domain interrupts that are provided per DMA channel, the AXIPCIE_MAIN.MSGF_DMA_MASK bits for each DMA channel should be set.