System Memory Virtualization Using SMMU Address Translation

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The SMMU translates the virtual addresses within each operating environment into physical addresses of the system and is described in this section. The transaction protection mechanism of the SMMU is described in System Protection Units.

Since the MPSoC system can support multiple operating systems with each guest OS supporting multiple application environments, the SMMU provides two stages of address translation. The first stage separates memory space for the operating systems and is managed by the hypervisor. The second stage separates application memory space within an OS and is managed by the host operating system. The programming of the address translation is coordinated with the MMUs in the MPCores and any MMUs in the PL to build the multitasking, heterogeneous system that shares one physically addressed memory subsystem.

First-stage hardware address translation for virtualized, multiple-guest operating systems. Virtual address (VA) to intermediate physical address (IPA).

°Hypervisor software programs the first-stage address translation unit to virtualize the addresses of bus masters other than the processors, e.g., DMA units and PL masters.

°Associates each bus master with its intermediate virtual memory space of its OS.

Second-stage hardware address translation for multi-application operating systems. Intermediate physical address (IPA) to physical address (PA).

°Guest OS software programs the second-stage translation unit to manage the addressing of the memory mapped resources for each application program.

°Associates the intermediate virtual memory address to the system’s physical address space.

The SMMU has the translation buffer and control units.

Note:   The SMMU TCU uses the same master ID as that the one used for R5_0 so the security protection units cannot differentiate between the two masters. To mitigate this issue coherency can be disabled for the RPU so R5_0 is forced to access DDR through S0 port and SMMU TCU to S1 and S2 ports.