System PLL Clock Units

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

Two system PLL clock units are in the LPD and three are in the FPD power domain. Each PLL unit has two clock dividers on its output; one in the LPD and one in the FPD. These clock dividers can provide two different clocking frequencies from one PLL (in the two clock domains). The PLL output and clock frequencies are specified in the Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics (DS925) [Ref 2]. The maximum clock output frequencies are somewhat lower for clocks crossing power domains.

Each system PLL unit has a suggested usage, but the individual clock generators can select from one of the three PLL clocks routed to it as defined by the registers listed in the Clock Generator Control Registers section.

The system PLL units reside in the LPD and FPD power domains:.

Low power domain system PLLs:

°I/O PLL (IOPLL): provides clocks for all low speed peripherals and part of the interconnect.

°RPU PLL (RPLL): provides clocks for the RPU MPCore and part of the interconnect.

Full-power domain system PLLs:

°APU PLL (APLL): provides clocks for the APU MPCore clock and part of the interconnect.

°Video PLL (VPLL): provides clocks for the video I/O.

°DDR PLL (DPLL): provides clocks for the DDR controller and part of the interconnect.

Note:   There are six DDR PHY PLLs in the DDR memory controller that are used for the DRAM address and control output signals, and the data and ECC byte lanes. The PHY PLLs are dedicated to the DDR I/O interface and cannot be used as a clock source for the clock generator units.

The five system PLLs (RPLL, IOPLL, APLL, DPLL, and VPLL) are powered by one voltage supply, VCC_PSPLL. The six DDR PLLs for the DRAM address/control and I/O byte lanes are powered by VCC_PSDDR_PLL.

It is possible to use the PLL output from one power domain in the other power domain. The IOPLL and RPLL output in the low-power domain (LPD) can be an input to the full-power domain (FPD) using a separate 6-bit programmable divider. Similarly, the APLL, DPLL, or VPLL output clock can be an input clock to individual 6-bit programmable dividers in the LPD. The 6-bit programmable divider are controlled using (for example) the crf_apb.APLL_TO_LPD_CTRL register.