System PLL Operation

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The voltage controlled oscillator (VCO) in the PLL synthesizes the output frequency based on the feedback multiplier. The VCO supports both fractional and integer multipliers. The fractional mode is enabled by setting xPLL_FRAC_CFG[ENABLED] to 1.

The VCO output frequency (FVCO) is determined using the following equation.

FVCO = FREFCLK x M.F

In this equation, the FREFCLK is an input reference clock frequency, M is the integer part of the multiplier value, and F is the fractional part.

The output frequency (FCLKOUT), after the divider stage, is determined by the following equation.

FCLKOUT = FVCO/O

In this equation, O is the output divider that can be set to 1 or 2.